With recent advancement of digital technologies, electronic hardware such as portable information devices and home information appliances have been developed to provide higher functionality. For this reason, demands for an increase in a capacity of nonvolatile memory elements, reduction in a write electric power in the memory elements, reduction in write/read time in the memory elements, and longer life of the memory elements have been increasing.
Under the circumstances in which there are such demands, it is said that there is a limitation on miniaturization of the existing flash memory using a floating gate. On the other hand, a nonvolatile memory element (resistance variable memory) using a resistance variable layer as a material of a memory section is formed by a memory element having a simple structure including a resistance variable element. Therefore, further miniaturization, a higher-speed, and lower electric power consumption of the nonvolatile memory elements are expected.
When using the resistance variable layer as the material of the memory section, its resistance value changes from a high-resistance value to a low-resistance value or from the low-resistance value to the high-resistance value, for example, by applying electric pulses thereto. In this case, it is necessary to clearly distinguish two values, which are the high-resistance value and the low-resistance value, to change the resistance value stably between the low-resistance value and the high-resistance value at a high-speed, and to retain these two values in a nonvolatile manner. For the purpose of stabilization of such memory characteristics and miniaturization of memory elements, a variety of proposals have been made in the past.
As one of such proposals, patent document 1 discloses memory elements in which memory cells are formed by resistance variable elements each of which includes two electrodes and a storing layer sandwiched between these electrodes and is configured to reversibly change a resistance value of the storing layer. FIG. 13 is a cross-sectional view showing a configuration of such a conventional memory element.
As shown in FIG. 13, the memory element has a configuration in which plural resistance variable elements 10 forming memory cells are arranged in an array form. The resistance variable element 10 has a configuration in which a high-resistance layer 2 and an ion source layer 3 are sandwiched between a lower electrode 1 and an upper electrode 4. The high-resistance layer 2 and the ion source layer 3 form a storing layer. The storing layer enables data to be stored in the resistance variable element 10 in each memory cell.
Each resistance variable element 10 is disposed above a MOS transistor 18 formed on a semiconductor substrate 11. The MOS transistor 18 includes source/drain regions 13 formed in a region isolated by an element isolating layer 12 inside the semiconductor substrate 11 and a gate electrode 14. The gate electrode 14 also serves as a word line which is one address wire of the memory element.
One of the source/drain regions 13 of the MOS transistor 18 is electrically connected to the lower electrode 1 of the resistance variable element 10 via a plug layer 15, a metal wire layer 16, and a plug layer 17. The other of the source/drain regions 13 of the MOS transistor 18 is connected to the metal wire layer 16 via the plug layer 15. The metal wire layer 16 is connected to a bit line which is the other address wire of the memory element.
By applying electric potentials with different polarities between the lower electrode 1 and the upper electrode 4 of the resistance variable element 10 configured as described above, ion source of the ion source layer 3 forming the storing layer is caused to migrate to the high-resistance layer 2. Or, the ion source is caused to migrate from the high-resistance layer 2 to the upper electrode 4. Thereby, the resistance value of the resistance variable element 10 changes from a high-resistance state value to a low-resistance state value, or from the low-resistance state value to the high-resistance state value, so that data is stored.
Examples using binary transition metal oxides which are different from the resistance variable materials disclosed in Patent document 1 are reported. For example, Patent document 2 discloses as resistance variable materials, NiO, V2O5, ZnO, Nb2O5, TiO2, WO3, and CoO.